A recent theme or trend in the design of electronic integrated circuits is toward reduced power consumption. Power consumption is a critical issue in integrated circuits and systems designed for use in portable computers, laptop computers, personal digital assistants, and similar devices that operate on battery power. One way to reduce power consumption is to design the integrated circuits for such systems to operate at a lower voltage level. For example, integrated circuits now are being designed to operate with a typical internal supply voltage V.sub.DD of 3.3 volts, rather than 5 volts as in past practice.
However, certain components of particular integrated circuits cannot operate at such reduced voltage levels. Therefore, some integrated circuits have an internal voltage pump circuit that raises the supply voltage to a boosted voltage level high enough to operate particular internal components. Accurate control of the boosted voltage level is important. For example, flash memory devices require a boosted voltage level that is controlled within a narrow range to ensure accurate writing of internal memory cells.
One prior voltage pump circuit 100 is shown in FIG. 1. An input signal SIG is coupled to the input terminal 2 of an inverter 10 that inverts the logic level of SIG. The inverted output is coupled to an input terminal 3 of an inverter 12, which is one in a series coupled chain 50 of inverters 12, 14, 16, 18, and 20. The output of inverter 14 is coupled by path 22 to one side of a first capacitor 26. The other side of the first capacitor 26 is coupled to the sources of n-channel transistors 28, 30, and to the gate of transistor 30 along path 23. The drains of the transistors 28, 30 are coupled to the supply voltage V.sub.DD ;. The gate of transistor 28 is also coupled to V.sub.DD. A storage capacitor 46 has one side coupled to a boosted voltage output signal VPPOUT and the other side coupled to V.sub.DD.
The right side the first capacitor 26 is also coupled to the gates of two transistors 32, 34. The gate of transistor 32 is further coupled to the gate of transistor 30 by path 23. The drain of each transistor 32, 34 is coupled to V.sub.DD. The output 24 of the last inverter 20 in the inverter chain 50 is coupled to the first side of both a second capacitor 38 and a third capacitor 40. The second side of the second capacitor 38 is coupled to the gate of an output driver transistor 42, as is the source of transistor 34. The second side of the third capacitor 40 is coupled to the drain of transistor 42. The second side of the third capacitor 40 is also coupled along path 41 to the source of transistor 32. The source terminal of transistor 42 is fed on an output path 44 as a boosted voltage output signal VPPOUT.
A transistor 36, having its gate and drain coupled to V.sub.DD, and its source coupled to the drain of the output driver transistor 42, forms a power-on pre-charging circuit for the third capacitor 40.
Transistors 28, , and 36 are n-channel power-on pre-charge transistors that are used to pre-charge capacitors 26 and 46, respectively. Thus, when V.sub.DD is supplied, transistors 28, 36 conduct and pass V.sub.DD, less the transistor threshold voltage drop Vth, to the right side of the first capacitor 26 and the storage capacitor 46, thereby pre-charging the first capacitor 26 and the storage capacitor 46 to a voltage level of V.sub.DD -Vth.
Transistor 30 operates as a clamp transistor that prevents the voltage level on path 23 from rising too high. Transistor 30 is normally off, and is turned on only when path 23 is boosted above a voltage level of V.sub.DD +Vth. When transistor 30 conducts, path 23 will fall toward the level of V.sub.DD. Transistor 42 is a pass transistor that transfers a maximum allowable charge to capacitor 46 when the gate and the drain of transistor 42 are both boosted via path 35 and path 41.
The circuit of FIG. 1 can be implemented in a metal oxide semiconductor (MOS) integrated circuit using known fabrication techniques. The signal SIG is a digital signal having a high logic level defined as about 3.3 volts and a low logic level defined as near ground potential. The signal SIG may be, for example, a clocked output signal from another component within an integrated circuit that contains the voltage pump circuit 100, as well as other components.
Operation of the circuit 100 can be understood with reference to FIG. 5, which is a timing diagram of waveforms produced by different parts of the circuit 100, in conjunction with FIG. 1. FIG. 5 shows a first waveform 500 that represents the SIG signal; a second waveform 502 that represents the voltage level of path 22; a third waveform 504 that represents the voltage level of path 24; a fourth waveform 506 that represents the voltage level of path 23; a fifth waveform 508 that represents the voltage level of path 35 and path 41; and a sixth waveform 510 that represents the voltage level of the output signal VPPOUT.
The first, second and third waveforms have a voltage level range from ground (GND) to V.sub.DD,, as shown by the vertical axis of FIG. 5. The range of the fourth waveform is from the level (V.sub.DD -Vth) to the level (2V.sub.DD -Vth). The range of the fifth waveform is from the level V.sub.DD to the level (2.sub.VDD).
The horizontal axis of FIG. 5 represents time. Five successive clock time intervals 512, 514, 516, 518, 520 are shown.
The voltage pump circuit 100 is operated by setting SIG to a low logic level, as shown by waveform 500 at clock interval 512. Beforehand, the circuit is turned on, which causes capacitor 26 to be pre-charged to the voltage level V.sub.DD -Vth. Then, when SIG is pulled low, the output of inverter 20 also will be low and the output of inverter 14 will be at a high logic level. Thus path 22 becomes high or equal to V.sub.DD, as shown by waveform 502 at clock interval 512. Between clock interval 512 and 514, the voltage level on path 23 rises. The final voltage level on path 23 is boosted to 2 V.sub.DD -Vth, that is, the sum of V.sub.DD on path 22 plus the initial pre-charged voltage across the first capacitor 26 This level is shown by waveform 506 at clock interval 514. Concurrently, path 24 will be at a low logic level or ground potential, as shown by waveform 504. When node 23 rises to a level of at least V.sub.DD +Vth, transistors 32 and 34 will turn on. When transistors 32 and 34 turn on, transistor 32 will conduct V.sub.DD to path 41 and transistor 34 will conduct V.sub.DD to path 35, as shown by waveform 508 at clock interval 514. Consequently, both the third capacitor 40 and the second capacitor 38 will be pre-charged to V.sub.DD. Thus, the effect of pulling SIG low is to pre-charge the second and third capacitors 38, 40. The time when SIG is low is known as the pre-charge phase.
When SIG is pulled high, the output of inverter 14 is low, path 22 is low, and the output of inverter 20 is high. This relationship is shown by waveforms 500, 502 and 504 between clock intervals 514 and 516. When the output of inverter 14 goes low, the left side of the first capacitor 26 will be low or at ground potential through path 22. The right side of the first capacitor 26 will be charged to V.sub.DD less Vth through transistor 28, as shown by waveform 506 at clock interval 516. At the same time, path 24 is high (at voltage level V.sub.DD), which causes paths 41 and 35 to be boosted to 2V.sub.DD,, as shown by waveform 508 at clock interval 516. The 2V.sub.DD boosted voltage level on path 35 is the sum of the initial pre-charged voltage level of V.sub.DD across capacitor 38 and the voltage level on path 24. Path 41 is boosted to 2 V.sub.DD in similar manner.
When both paths 35 and 41 are boosted, an incremental amount of charge is transferred into the storage capacitor 46, as indicated by waveform 510. Since SIG is a clock signal, during each clock cycle an additional amount of charge is added into and stored by capacitor 46. As more charge builds up in capacitor 46, the voltage level of the output VPPOUT gradually rises, as shown by waveform 510, and continues to rise until it reaches a saturation level. Accordingly, the time when SIG is high is known as the boost phase.
Normally, VPPOUT is greater than V.sub.DD. VPPOUT typically is at least V.sub.DD +Vth, and can vary depending on the operating conditions of the circuit 100. Since VPPOUT is usually higher than V.sub.DD, VPPOUT is sometimes called super- V.sub.DD.
Although this approach produces an output signal with a voltage that is boosted with respect to the input voltage, this circuit and other known voltage pump circuits have several significant disadvantages. For example, if the foregoing circuit is used to drive a large number of pins that are all being written or driven at a high logic level (that is, a condition which draws charge from capacitor 46), the boosted voltage level is greatly reduced due to the load imposed by the large number of pins. Under some conditions, the boosted voltage dips so low under multiple-pin loading that it is below the defined logic high level for the driven pins, and is therefore insufficient to drive the output pins. This can cause unexpected adverse chip performance; for example, a chip with sixteen output pins may work when two pins are driven high, but fail when all sixteen are driven high.
Other problems arise when a large number of output pins all are driven low (that is, a condition which draws little or no charge from capacitor 46) in a chip having the foregoing voltage pump circuit. In that case, the boosted voltage provided by the voltage pump circuit is unused, which wastes power. In addition, if the voltage pump continues to add charge to capacitor 46 and the load connected to the node VPPOUT does not withdraw charge from capacitor 46, then the level of VPPOUT can rise to a level which will excessively stress the silicon used to fabricate the chip.
Each of these problems becomes worse when a larger number of output pins is used in a chip, that is, when the bandwidth of the chip is increased. The problems described above will be significantly worse in a chip having 64 pins driven with a boosted voltage compared to a chip with eight pins. Thus, adverse performance by a voltage pump circuit can become a critical factor that limits improvement of low-voltage, low-power integrated circuits.